ARM ARM7TDMI - Page 221

Debug in Depth
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-11
B.5.5 CLAMP (b0101)
This instruction connects a single-bit shift register, the BYPASS register, between TDI
and TDO. When the CLAMP instruction is loaded into the instruction register, the state
of all the scan cell output signals is defined by the values previously loaded into the
currently loaded scan chain. This instruction must only be used when scan chain 0 is the
currently selected scan chain:
• In the CAPTURE-DR state, a 0 is captured by the bypass register.
• In the SHIFT-DR state, test data is shifted into the bypass register using TDI and
out using TDO after a delay of one TCK cycle. The first bit shifted out is a 0.
• In the UPDATE-DR state the bypass register is not affected.
B.5.6 HIGHZ (b0111)
This instruction connects a single-bit shift register, the BYPASS register, between TDI
and TDO. When the HIGHZ instruction is loaded into the instruction register, the
Address bus, A[31:0], the data bus, D[31:0], nRW, nOPC, LOCK, MAS[1:0], and
nTRANS are all driven to the high impedance state and the external HIGHZ signal is
driven HIGH. This is as if the signal TBE had been driven LOW:
• In the CAPTURE-DR state, a 0 is captured by the bypass register.
• In the SHIFT-DR state, test data is shifted into the bypass register using TDI and
out using TDO after a delay of one TCK cycle. The first bit shifted out is a 0.
• In the UPDATE-DR state, the bypass register is not affected.
B.5.7 CLAMPZ (b1001)
This instruction connects a single-bit shift register, the BYPASS register, between TDI
and TDO.
When the CLAMPZ instruction is loaded into the instruction register, all the tristate
outputs are placed in their inactive state, but the data supplied to the scan cell outputs is
derived from the scan cells. The purpose of this instruction is to ensure that, during
production test, each output can be disabled when its data value is either 0 or 1:
• In the CAPTURE-DR state, a 0 is captured by the bypass register.
• In the SHIFT-DR state, test data is shifted into the bypass register using TDI and
out using TDO after a delay of one TCK cycle. The first bit shifted out is a 0.
• In the UPDATE-DR state, the bypass register is not affected.