Debug in Depth
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-13
When the BYPASS instruction is loaded into the instruction register, all the scan cells
assume their normal system mode of operation. The BYPASS instruction has no effect
on the system pins:
• In the CAPTURE-DR state, a 0 is captured the bypass register.
• In the SHIFT-DR state, test data is shifted into the bypass register through TDI
and shifted out through TDO after a delay of one TCK cycle. The first bit to shift
out is a 0.
• In the UPDATE-DR state, the bypass register is not affected.
All unused instruction codes default to the BYPASS instruction.
Note
BYPASS does not enable the processor to exit debug state or synchronize to MCLK for
a system-speed access while in debug state. You must use RESTART to achieve this.
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