ARM ARM7TDMI - Page 229

Debug in Depth
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-19
Note
During RUN-TEST-IDLE, the core is not clocked.
The operation can then be repeated.
Scan chain 1
The primary use for scan chain 1 is for debugging, although it can be used for EXTEST
on the data bus. Scan chain 1 is selected using the SCAN_N TAP controller instruction.
Debugging is similar to INTEST and the procedure described above for scan chain 0
must be followed.
Scan chain 1 is 33 bits long, 32 bits for the data value, plus the scan cell on the
BREAKPT core input. This 33rd bit serves four purposes:
1. Under normal INTEST test conditions, it enables a known value to be scanned
into the BREAKPT input.
2. During EXTEST test conditions, the value applied to the BREAKPT input from
the system can be captured.
3. While debugging, the value placed in the 33rd bit determines if the ARM7TDMI
core synchronizes back to system speed before executing the instruction. See
System speed access on page B-32 for further details.
4. After the ARM7TDMI core has entered debug state, the first time this bit is
captured and scanned out, its value tells the debugger if the core entered debug
state because of a breakpoint (bit [33] clear) or a watchpoint (bit [33] set).
Scan chain 2
Purpose Enables the EmbeddedICE-RT macrocell registers to be accessed. The
order of the scan chain, from TDI to TDO is:
1. Read/write, register address bits 4 to 0.
2. Data value bits 31 to 0.
See EmbeddedICE-RT block diagram on page B-43.
Length 38 bits.
To access this serial register, scan chain 2 must first be selected using the SCAN_N TAP
controller instruction. The TAP controller must then be placed in INTEST mode.
• During CAPTURE-DR, no action is taken.