ARM ARM7TDMI - Page 236

Debug in Depth
B-26 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
B.8.2 Determining system state
To meet the dynamic timing requirements of the memory system, any attempt to access
system state must occur synchronously to it. The ARM7TDMI core must be forced to
synchronize back to system speed. This is controlled by bit [33] (BREAKPT) of scan
chain 1 (see Figure B-1 on page B-4).
Any instruction can be placed in scan chain 1, and its execution speed depends on the
state of bit [33] as follows:
Bit [33] clear Instructions are executed at debug speed.
Bit[ 33] set Instructions are executed at system speed, with the exception of
the instruction that is executing when the state of bit [33] is
changed.
After a system-speed instruction has been scanned into the data bus and clocked into the
pipeline, the RESTART instruction must be loaded into the TAP controller. This causes
the ARM7TDMI core to behave as follows:
1. The ARM7TDMI core automatically synchronizes back to MCLK, the system
clock.
2. It executes the instruction at system speed.
3. It re-enters debug state.
4. It switches itself back to the internally-generated DCLK.
When the instruction has completed, DBGACK is HIGH and the core is switched back
to DCLK. At this point, INTEST can be selected in the TAP controller and debugging
can resume.
To determine that a system-speed instruction has completed, the debugger must look at
both DBGACK and nMREQ. To access memory, the ARM7TDMI core drives
nMREQ LOW, after it has synchronized back to system speed. This transition is used
by the memory controller to arbitrate if the ARM7TDMI core can have the bus in the
next cycle. If the bus is not available, the core can have its clock stalled indefinitely. The
only way to tell that the memory access has completed is to examine the state of both
nMREQ and DBGACK. When both are HIGH, the access has completed. Usually, the
debugger uses the EmbeddedICE-RT macrocell to control debugging. By reading the
EmbeddedICE-RT macrocell status register, the state of nMREQ and DBGACK can
be determined.
The debug host can determine the system memory state using:
• system-speed load multiple instructions
• debug-speed store multiple instructions.