ARM ARM7TDMI - Page 274

Differences Between Rev 3a and Rev 4
C-4 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
C.2.3 Enhancement to ETM interface
An extra output signal has been added to the ETM interface on the ARM7TDMI Rev 4,
to improve program execution trace. This signal is INSTRVALID, and it connects
directly to the pin of the same name on ETM7 Rev 1.
C.2.4 Improvement in Debug Communications Channel bandwidth
In ARM7TDMI Rev 3a, two accesses to scan chain 2 were required to read the DCC
data. The first accessed the status bit, and the second accessed the data itself.
To improve performance, only one access is required to read both the data and the status
bit, in the ARM7TDMI Rev 4 because the status bit is now included in the LSB of the
address field which is read from the scan chain.
The status bit in the DCC control register is left unchanged to ensure backwards
compatibility.
C.2.5 Access to Debug Communications Channel through JTAG
The DCC control register can be controlled from the JTAG interface in ARM7TDMI
Rev 4. A write clears bit [0], the data read control bit.
C.2.6 Alterations to TAP controller scan chain
The alterations to the TAP controller scan chain are as follows:
TAP controller ID register
The TAP controller ID register value is now
0x40700F0F .
Scan chain 0 The output scan cells now include an update stage so that the
output pins of the ARM7TDMI do not toggle as shifted data is
scanned around the chain.
This scan chain also now includes all the I/O pins of the
ARM7TDMI (except for the TAP related ports that cannot be
scanned, for example TAPS M, TDI, and TDO). Previous
versions of the ARM7TDMI did not include pins associated with
the EmbeddedICE logic.
The additional I/O pins that are now included in scan chain 0 are:
• DBGRQI
• COMMRX
• COMMTX
• nENOUTI