Programmer’s Model
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 2-17
2.8.2 Entering an exception
The ARM7TDMI processor handles an exception as follows:
1. Preserves the address of the next instruction in the appropriate LR.
When the exception entry is from ARM state, the ARM7TDMI processor copies
the address of the next instruction into the LR, current PC+4 or PC+8 depending
on the exception.
When the exception entry is from Thumb state, the ARM7TDMI processor writes
the value of the PC into the LR, offset by a value, current PC+4 or PC+8
depending on the exception, that causes the program to resume from the correct
place on return.
The exception handler does not have to determine the state when entering an
exception. For example, in the case of a SWI,
MOVS PC, r14_svc
always returns to
the next instruction regardless of whether the SWI was executed in ARM or
Thumb state.
2. Copies the CPSR into the appropriate SPSR.
3. Forces the CPSR mode bits to a value that depends on the exception.
4. Forces the PC to fetch the next instruction from the relevant exception vector.
The ARM7TDMI processor can also set the interrupt disable flags to prevent otherwise
unmanageable nestings of exceptions.
FIQ
SUBS PC, R14_fiq, #4
PC+4 PC+4 Where PC is the address of the instruction
that was not executed because the FIQ or
IRQ took priority
IRQ
SUBS PC, R14_irq, #4
PC+4 PC+4
DABT
SUBS PC, R14_abt, #8
PC+8 PC+8 Where PC is the address of the Load or Store
instruction that generated the Data Abort
RESET Not applicable - - The value saved in r14_svc upon reset is
unpredictable
Table 2-3 Exception entry and exit (continued)
Exception
or entry
Return instruction
Previous state ARM r14_x
Thumb r14_x
Remarks
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