HP 8560A

Flatness Control (RF Gain DACs)
See function block M of A3 Interface Assembly Schematic Diagram (sheet 4 of 6).
RF Gain DACs control the Al5 assembly’s flatness compensation amplifiers. The RF Gain
DACs are arranged so that the output of one DAC is the voltage reference for the other DAC.
This results in an RF GAIN voltage which is exponentially proportional to the DAC settings.
Each DAC is set to the same value. The Al5 RF assembly converts the RF GAIN signal to
a current for driving the PIN diode attenuators in the Flatness Compensation Amplifiers.
The exponentially-varying voltage compensates for the nonlinear resistance-versus-current
characteristic of the PIN diodes.
1. Place the WR PROT/WR ENA jumper on the A2 Controller assembly in the WR ENA
position.
2. Press ICAL), MORE 1 OF 2 ,
SERVICE CAL DATA, FLATNESS, FLATNESS DATA. Press
NEXT BAND until “FLATNESS BAND # 0” is displayed.
3. Press the @ key until “DATA @ 300 MHz” is displayed. Note the number directly below
“DATA @ 300 MHz”; this is the RF Gain DAC value.
4. Connect a positive DVM lead to A3J400 pin 13 and the negative DVM lead to A3TP4.
5. Check that the DVM reading increases from near 0 Vdc to between +3.5 and +5.0 Vdc as
the RF Gain DAC setting is increased from 0 to 255.
6. If the DVM readings are incorrect, press [m),(E), SINGLE,a, MORE 1 OF 2,
SERVICE CAL DATA, FLATNESS ,and FLATNESS DATA. Press NEXT BAND until
“FLATNESS BAND # 0” is displayed. Press the @ key until “DATA @ 300 MHz” is
displayed. Proceed as follows:
a. Check the +lO V reference.
b. Check for pulses at A3U417 pin 16 (LWRCLK).
c. While rotating the front-panel knob, check for pulses at A3U417 pin 15 (LDACl).
d. While rotating the front-panel knob, check for pulses at U417 pin 6 (IAO).
7. The LWRCLK and LDACl are incorrect, refer to the Interface Strobe Select block in this
chapter.
8. Place the WR PROT/ WR ENA jumper on the A2 Controller assembly in the WR PROT
position.
ADC/lnterface Section 7-11