4. Step the Video BW down to
.1
Hz. At each step, the amplitude of the LO feedthrough
should decrease.
5. Refer to Table 7-7 and check for correct latch settings for the selected video bandwidth
setting.
6. If latch
A3U102’s
output is not correct, trigger an oscilloscope on
LLOGSTB
(UlO2 pin 9)
and monitor
U102
pin 1 and other latch inputs while changing the video bandwidth.
7. If the inputs are incorrect, troubleshoot the analog bus. Correct inputs with bad outputs
indicate a faulty
U102.
8. Check that the outputs of
A3UlllA,
ASUlllB,
and
A3U107A/B/C/D
are correct for
their inputs. The outputs should be high with noninverting inputs higher than the
+1.4
V
threshold voltage. If a voltage drop is noticed across these components, suspect A3CR109
or A3Q317B. Since no dc current flows through any of the series resistances or FETS
(drain to source), no voltage drops should occur.
Table 7-7. A3U102 Latch Outputs
Video BW
300
Hz
1kHz
3
kHz
10kHz
30kHz
100
kHz
300
kHz
1MHz
3 MHz
Pin2
H
L
L
L
H
L
L
L
L
Pin 5
L
L
H
L
L
L
H
L
L
Pin 7
L
L
L
L
H
H
H
H
L
Pin 10 Pin 12
L
L
L
L
L
L
L
H
L
L
L L
L
L
L
H
H
L
Pin 15
L
H
L
L
L
H
L
L
L
Video Filter Buffer Amplifier
See function block W of A3 Interface Assembly Schematic Diagram (sheet 5 of 6).
The video filter buffer amplifier provides outputs for video trigger, positive and negative
peak detectors, and the analog zero-span (sweeps
<30
ms). The zero-span video
output is terminated in 500 ohms on the A2 Controller assembly. The amplifier is a
high-input-impedance buffer amplifier with a gain of one when properly terminated.
Current source U307C provides twice the current of Q316. Resistor R145 and current source
U307D shift the dc level. Resistor R260 terminates the peak detector inputs in 500 ohms. The
unterminated gain is 1.1. Diode CR114 prevents
latchup
during positive overdrive conditions
while CR113 protects Q318 during overdrive.
Diode CR117 is a 12.7 V zener that limits the
peak detector’s output to
t1.5
V. Typically, limiting occurs at
+l.l
V.
7-16
ADC/lnterface
Section