Intel Cyclone 10 GX User Manual

Figure 55. Architecture of 10M/100M/1G/2.5G/5G/10G (USXGMII) Configuration
Soft PCS
Configuration
registers
Reconfiguration Block
Avalon-MM
Interface
TX
32-bit XGMII
10M/100M/1G/2.5G/5G/10G Multi-rate Ethernet PHY
Native PHY Hard IP
TX Serial
RX Serial
Hard IP
Soft Logic
Legend
Intel Stratix 10 FPGA Device
LL Ethernet
10G MAC
User
Application
PLL
for 10 GbE
RX
322-MHz or 644-MHz
Reference Clock
External
PHY
Transceiver
Reset
Controller
32-bit XGMII
Avalon-ST
Interface
Hard PCS
PMA
In the transmit direction, the PHY encodes the Ethernet frame as required for reliable
transmission over the media to the remote end. In the receive direction, the PHY
passes frames to the MAC.
Note: You can generate the MAC and PHY design example using the Low Latency Ethernet
10G MAC Intel FPGA IP Parameter Editor.
The IP core includes the following interfaces:
• Datapath client-interface:
— 10M/100M/1G/2.5G/5G/10G (USXGMII)—XGMII, 32 bits
• Management interface—Avalon-MM host slave interface for PHY management.
• Datapath Ethernet interface with the following available options:
— 10M/100M/1G/2.5G/5G/10G (USXGMII) —Single 10.3125 Gbps serial link
• Transceiver PHY dynamic reconfiguration interface—an Avalon-MM interface to
read and write the Intel Cyclone 10 GX Native PHY IP core registers. This interface
supports dynamic reconfiguration of the transceiver. It is used to configure the
transceiver operating modes to switch to desired Ethernet operating speeds.
The 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration supports the following
features:
• USXGMII—10M/100M/1G/2.5G/5G/10G speeds
• Full duplex data transmission
• USXGMII Auto-Negotiation
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English