2.6.3.3.1. Clocking and Reset Sequence
Clocking Requirements:
• For 32-bit XGMII, the 312.5 MHz clock must have zero ppm difference with
reference clock of 10G transceiver PLL. Therefore, the 312.5 MHz clock must
derived from the transceiver 10G reference clock for 10M/100M/1G/2.5G/5G/10G
(USXGMII) variant.
The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP core for Intel Cyclone 10
GX devices supports up to ±100 ppm clock frequency difference.
2.6.3.3.2. Timing Constraints
Constrain the PHY based on the fastest speed. For 10M/100M/1G/2.5G/5G/10G
(USXGMII) operating mode, constraint it based on 10G.
Table 105. Timing Constraints
PHY Configuration Constrain PHY for
10M/100M/1G/2.5G/5G/10G (USXGMII) 10G datapath
2.6.3.3.3. Switching Operation Speed
Table 106. Supported Operating Speed
PHY
Configuratio
ns
Features 10M 100M 1G 2.5G 5G 10G
10M/
100M/1G/
2.5G/5G/10
G (USXGMII)
Protocol
10GBASE-R
1000x data
replication
10GBASE-R
100x data
replication
10GBASE-R
10x data
replication
10GBASE-R
4x data
replication
10GBASE-R
2x data
replication
10GBASE-R
No data
replication
Transceiver
Data Rate
(21)
10.3125
Gbps
10.3125
Gbps
10.3125
Gbps
10.3125
Gbps
10.3125
Gbps
10.3125
Gbps
MAC
Interface
32-bit XGMII
@ 312.5 MHz
32-bit XGMII
@ 312.5 MHz
32-bit XGMII
@ 312.5 MHz
32-bit XGMII
@ 312.5 MHz
32-bit XGMII
@ 312.5 MHz
32-bit XGMII
@ 312.5 MHz
2.6.3.4. Configuration Registers
You can access the 32-bit configuration registers via the Avalon-MM interface.
Observe the following guidelines when accessing the registers:
• Do not write to reserved or undefined registers.
• When writing to the registers, perform read-modify-write to ensure that reserved
or undefined register bits are not overwritten.
(21)
With oversampling for lower data rates.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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