Intel Cyclone 10 GX User Manual

Table 107. Types of Register Access
Access Definition
RO Read only.
RW Read and write.
RWC Read, and write and clear. The user application writes 1 to the register bit(s) to invoke a defined
instruction. The IP core clears the bit(s) upon executing the instruction.
Table 108. PHY Register Definitions
Addr Name Description Access HW Reset
Value
0x400
usxgmii_control
Control Register — —
Bit [0]: USXGMII_ENA:
• 0: 10GBASE-R mode
• 1: USXGMII mode
RW 0x0
Bit [1]: USXGMII_AN_ENA is used when USXGMII_ENA
is set to 1:
• 0: Disables USXGMII Auto-Negotiation and manually
configures the operating speed with the
USXGMII_SPEED register.
• 1: Enables USXGMII Auto-Negotiation, and
automatically configures operating speed with link
partner ability advertised during USXGMII Auto-
Negotiation.
RW 0x1
Bit [4:2]: USXGMII_SPEED is the operating speed of
the PHY in USXGMII mode and USE_USXGMII_AN is set
to 0.
• 3’b000: 10M
• 3’b001: 100M
• 3’b010: 1G
• 3’b011: 10G
• 3’b100: 2.5G
• 3’b101: 5G
• 3’b110: Reserved
• 3’b111: Reserved
RW 0x0
Bit [8:5]: Reserved — —
Bit [9]: RESTART_AUTO_NEGOTIATION
Write 1 to restart Auto-Negotiation sequence The bit is
cleared by hardware when Auto-Negotiation is
restarted.
RWC
(hardw
are
self-
clear)
0x0
Bit [15:10]: Reserved — —
Bit [30:16]: Reserved — —
0x401
usxgmii_status
Status Register — —
Bit [1:0]: Reserved — —
Bit [2]: LINK_STATUS indicates link status for USXGMII
all speeds
• 1: Link is established
• 0: Link synchronization is lost, a 0 is latched
RO 0x0
Bit [3]: Reserved — —
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English