Intel Cyclone 10 GX

Addr Name Description Access HW Reset
Value
Bit [4]: Reserved — —
Bit [5]: AUTO_NEGOTIATION_COMPLETE
A value of 1 indicates the Auto-Negotiation process is
completed.
RO 0x0
Bit [15:6]: Reserved — —
Bit [31:16]: Reserved — —
0x402:0x404 Reserved — — —
0x405
usxgmii_partner_
ability
Device abilities advertised to the link partner during
Auto-Negotiation
— —
Bit [0]: Reserved — —
Bit [6:1]: Reserved — —
Bit [7]: EEE_CLOCK_STOP_CAPABILITY
Indicates whether or not energy efficient ethernet (EEE)
clock stop is supported.
• 0: Not supported
• 1: Supported
RO 0x0
Bit [8]: EEE_CAPABILITY
Indicates whether or not EEE is supported.
• 0: Not supported
• 1: Supported
RO 0x0
Bit [11:9]: SPEED
• 3'b000: 10M
• 3'b001: 100M
• 3'b010: 1G
• 3'b011: 10G
• 3'b100: 2.5G
• 3'b101: 5G
• 3'b110: Reserved
• 3'b111: Reserved
RO 0x0
Bit [12]: DUPLEX
Indicates the duplex mode.
• 0: Half duplex
• 1: Full duplex
RO 0x0
Bit [13]: Reserved — —
Bit [14]: ACKNOWLEDGE
A value of 1 indicates that the device has received three
consecutive matching ability values from its link partner.
RO 0x0
Bit [15]: LINK
Indicates the link status.
• 0: Link down
• 1: Link up
RO 0x0
Bit [31:16]: Reserved — —
0x406:0x411 Reserved — — —
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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