Intel Cyclone 10 GX User Manual

Addr Name Description Access HW Reset
Value
0x412
usxgmii_link_tim
er
Auto-Negotiation link timer. Sets the link timer value in
bit [19:14] from 0 to 2 ms in approximately 0.05 ms
steps. You must program the link timer to ensure that it
matches the link timer value of the external NBASE-T
PHY IP Core.
The reset value sets the link timer to approximately 1.6
ms.
Bits [13:0] are reserved and always set to 0.
[19:14
]: RW
[13:0]:
RO
[19:14]:
0x1F
[13:0]:
0x0
0x413:0x41F Reserved — — —
0x461
phy_serial_loopb
ack
Configures the transceiver serial loopback in the PMA
from TX to RX.
— —
Bit [0]
• 0: Disables the PHY serial loopback
• 1: Enables the PHY serial loopback
RW 0x0
Bit [15:1]: Reserved — —
Bit [31:16]: Reserved — —
2.6.3.5. Interface Signals
Figure 56. PHY Interface Signals
PHY
reset
tx_digitalreset
rx_digitalreset
tx_analogreset
rx_analogreset
Reset
csr_clk
csr_address[10:0]
csr_write
csr_read
csr_writedata[32]
csr_readdata[32]
csr_waitrequest
Avalon-MM
Control & Status
Interface
rx_is_lockedtodata
tx_cal_busy
rx_cal_busy
Transceiver Status &
Reconfiguration Interface
reconfig_clk
reconfig_write
reconfig_address[9:0]
reconfig_reset
reconfig_readdata[31:0]
reconfig_writedata[31:0]
reconfig_read
reconfig_waitrequest
Intel
Cyclone
10 GX
operating_speed[2:0]
xgmii_tx_control[3:0]
xgmii_tx_data[31:0]
xgmii_tx_coreclkin
TX XGMII
xgmii_rx_control[3:0]
xgmii_rx_data[31:0]
xgmii_rx_coreclkin
RX XGMII
Status
Interface
led_an
rx_block_lock
tx_serial_clk
tx_serial_data
rx_serial_data
Serial
Interface
rx_cdr_refclk1
rx_pma_clkout
xgmii_tx_valid
xgmii_rx_valid
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English