2.6.3.5.1. Clock and Reset Signals
Table 109. Clock and Reset Signals
Signal Name Direction Width Description
Clock signals
csr_clk
Input 1 Clock for the Avalon-MM control and status
interface. Intel recommends 125 – 156.25 MHz for
this clock.
xgmii_tx_coreclkin
Input 1 XGMII TX clock. Provides timing reference and
312.5 MHz for 10M/100M/1G/2.5G/5G/10G
(USXGMII) mode. Synchronous to
tx_serial_clk with zero ppm.
xgmii_rx_coreclkin
Input 1 XGMII RX clock. Provides timing reference and
312.5 MHz for 10M/100M/1G/2.5G/5G/10G
(USXGMII) mode.
tx_serial_clk
Input 1 Serial clock from transceiver PLLs.
• 10M/100M/1G/2.5G/5G/10G (USXGMII) mode:
Provide 5156.25 MHz to this input port.
rx_cdr_refclk_1
Input 1 RX CDR reference clock for 10GbE. The frequency
of this clock can be either 322.265625 MHz or
644.53125 MHz, as specified by the Reference
clock frequency for 10 GbE (MHz) parameter
setting.
rx_pma_clkout
Output 1 Recovered clock from CDR, operates at the
following frequency:
• 10GbE: 322.265625 MHz
Reset signals
reset
Input 1 Active-high global reset. Assert this signal to
trigger an asynchronous global reset.
tx_analogreset
Input 1 Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an
asynchronous reset to the analog block on the TX
path.
tx_digitalreset
Input 1 Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an
asynchronous reset to the digital logic on the TX
path.
rx_analogreset
Input 1 Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an
asynchronous reset to the receiver CDR.
rx_digitalreset
Input 1 Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an
asynchronous reset to the digital logic on the RX
path.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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