Intel Cyclone 10 GX User Manual

2.6.3.5.2. Operating Mode and Speed Signals
Table 110. Transceiver Mode and Operating Speed Signals
Signal Name Direction Width Description
operating_speed
Output 3 Connect this signal to the MAC. This signal
provides the current operating speed of the PHY:
• 0x0 = 10G
• 0x1 = 1G
• 0x2 = 100M
• 0x3 = 10M
• 0x4 = 2.5G
• 0x5 = 5G
2.6.3.5.3. XGMII Signals
The XGMII supports 10GbE at 312.5 MHz.
Table 111. XGMII Signals
Signal Name Direction Width Description
TX XGMII signals—synchronous to xgmii_tx_coreclkin
xgmii_tx_data
Input 32 TX data from the MAC. The MAC sends the data in
the following order: bits[7:0], bits[15:8], and so
forth.
The width is:
• 32 bits for 10M/100M/1G/2.5G/5G/10G
configurations.
xgmii_tx_control
Input 4 TX control from the MAC:
•
xgmii_tx_control[0] corresponds to
xgmii_tx_data[7:0]
•
xgmii_tx_control[1] corresponds to
xgmii_tx_data[15:8]
• and so forth.
The width is:
• 4 bits for 10M/100M/1G/2.5G/5G/10G
configurations.
xgmii_tx_valid
Input 1
Indicates valid data on xgmii_tx_control and
xgmii_tx_data from the MAC.
Your logic/MAC must toggle the valid data as
shown below:
Speed Toggle Rate
10M Asserted once every
1000 clock cycles
100M Asserted once every
100 clock cycles
1G Asserted once every 10
clock cycles
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English