Intel Cyclone 10 GX User Manual

Signal Name Direction Width Description
Speed Toggle Rate
2.5G Asserted once every 4
clock cycles
5G Asserted once every 2
clock cycles
10G Asserted in every clock
cycle
RX XGMII signals—synchronous to xgmii_rx_coreclkin
xgmii_rx_data
Output 32 RX data to the MAC. The PHY sends the data in the
following order: bits[7:0], bits[15:8], and so forth.
The width is:
• 32 bits for 10M/100M/1G/2.5G/5G/10G
(USXGMII) configurations.
xgmii_rx_control
Output 4 RX control to the MAC.
•
xgmii_rx_control[0] corresponds to
xgmii_rx_data[7:0]
•
xgmii_rx_control[1] corresponds to
xgmii_rx_data[15:8]
• and so forth.
The width is:
• 4 bits for 10M/100M/1G/2.5G/5G/10G
(USXGMII) configurations.
xgmii_rx_valid
Output 1
Indicates valid data on xgmii_rx_control and
xgmii_rx_data from the MAC.
The toggle rate from the PHY is shown in the table
below.
Note: The toggle rate may vary when the start of
a packet is received or when rate match
occurs inside the PHY. You should not
expect the valid data pattern to be fixed.
Speed Toggle Rate
10M Asserted every 1000
clock cycles
100M Asserted every 100
clock cycles
1G Asserted once every 10
clock cycles
2.5G Asserted once every 4
clock cycles
5G Asserted once every 2
clock cycles
10G Asserted in every clock
cycle
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Send Feedback
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
119

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English