Intel Cyclone 10 GX User Manual

2.6.3.5.4. Status Signals
Table 112. Status Signals
Signal Name Direction Clock
Domain
Width Description
led_an
Output Synchronous
to
rx_clkout
1 Asserted when auto-negotiation is
completed.
rx_block_lock
Output Synchronous
to
rx_clkout
1 Asserted when the link synchronization for
10GbE is successful.
2.6.3.5.5. Serial Interface Signals
The serial interface connects to an external device.
Table 113. Serial Interface Signals
Signal Name Direction Width Description
tx_serial_data
Output 1 TX data.
rx_serial_data
Input 1 RX data.
2.6.3.5.6. Transceiver Status and Reconfiguration Signals
Table 114. Control and Status Signals
Signal Name Direction Width Description
rx_is_lockedtodata
Output 1 Asserted when the CDR is locked to the RX data.
tx_cal_busy
Output 1 Asserted when TX calibration is in progress.
rx_cal_busy
Output 1 Asserted when RX calibration is in progress.
Transceiver reconfiguration signals for Cyclone 10 GX devices
reconfig_clk
Input 1 Reconfiguration signals connected to the
reconfiguration block. The reconfig_clk signal
provides the timing reference for this interface.
reconfig_reset
Input 1
reconfig_address
Input 10
reconfig_write
Input 1
reconfig_read
Input 1
reconfig_writedata
Input 32
reconfig_readdata
Output 32
reconfig_waitrequest
Output 1
2.6.3.5.7. Avalon-MM Interface Signals
The Avalon-MM interface is an Avalon-MM slave port. This interface uses word
addressing and provides access to the 16-bit configuration registers of the PHY.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English