Intel Cyclone 10 GX User Manual

Figure 112. Signals and Ports of Native PHY IP for Basic, Basic with Rate Match
Configurations
reconfig_reset
reconfig_clk
reconfig_avmm
tx_digital_reset
tx_datak
tx_parallel_data[7:0]
tx_clkout
tx_datak
tx_parallel_data[7:0]
tx_coreclkin
tx_clkout
unused_tx_parallel_data[118:0]
Reconfiguration
Registers
TX Standard PCS
rx_datak
rx_parallel_data[7:0]
rx_clkout
rx_coreclkin
rx_errdetect
rx_disperr
rx_runningdisp
rx_patterndetect
rx_syncstatus
rx_rmfifostatus (1)
unused_rx_parallel_data[113:0]
RX Standard PCS
Nios Hard
Calibration IP
TX PMA
Serializer
RX PMA
Deserializer CDR
tx_cal_busy
rx_cal_busy
tx_serial_data
rx_serial_data
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
Central/Local
Clock Divider
tx_serial_clk0 (from TX PLL)
tx_analog_reset
rx_analog_reset
rx_digital_reset
rx_datak
rx_parallel_data[7:0]
rx_clkout
rx_errdetect
rx_disperr
rx_runningdisp
rx_patterndetect
rx_syncstatus
rx_rmfifostatus (1)
10
10
Cyclone 10 Transceiver Native PHY
Note:
1. Only applies when using the Basic with Rate Match transceiver configuration rule.
5. Instantiate and configure your PLL.
6. Create a transceiver reset controller.
7. Connect the Native PHY IP to the PLL IP and the reset controller. Use the
information in Transceiver Native PHY Ports for the Protocol to connect the ports.
Figure 113. Connection Guidelines for a Basic/Custom Design
reset
Pattern
Generator
Pattern
Checker
PLL IP
Reset
Controller
Cyclone 10
Transceiver
Native
PHY
tx_parallel_data
tx_datak
tx_clkout
pll_ref_clk
reset
tx_serial_clk
pll_locked
pll_powerdown
rx_ready
tx_ready
clk
reset
tx_digital_reset
tx_analog_reset
rx_digital_reset
rx_analog_reset
rx_is_lockedtoref
rx_is_lockedtodata
rx_parallel_data
rx_datak
rx_clkout
reconfig_clk
reconfig_reset
reconfig_write
tx_serial_data
rx_serial_data
For
Reconfiguration
rx_cdr_refclk
reconfig_read
reconfig_address
reconfig_writedata
reconfig_readdata
reconfig_waitrequest
cal_busy
8. Simulate your design to verify its functionality.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
181

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English