Intel Cyclone 10 GX

Figure 152. Resetting the Transceiver Channel During Device Operation
Device Power Up
pll_cal_busy
tx_analogreset
pll_locked
tx_digitalreset
1 3
tx_cal_busy
rx_cal_busy
pll_powerdown
5 6
4
rx_is_lockedtodata
rx_digitalreset
rx_analogreset
t
req
= 70 μs
t
req
t
req
2
t
LTD
min 4 μs
rx_digitalreset
t
min 70 μs
4.3.1.1.4. Dynamic Reconfiguration of Channel Using the Default Model
TX Channel
The numbers in this list correspond to the numbers in the following figure.
1.
Assert tx_analogreset, pll_powerdown, and tx_digitalreset, while
pll_cal_busy and tx_cal_busy are low.
2. Perform dynamic reconfiguration after minimum 70 μs of asserting
tx_analogreset.
3.
Deassert pll_powerdown after performing a dynamic reconfiguration.
Deassert tx_analogreset. This step can be done at the same time or after you
deassert pll_powerdown.
4.
The pll_locked signal goes high after the TX PLL acquires lock. Wait for
minimum 70 μs after deasserting tx_analogreset to monitor the pll_locked
signal.
5.
Deassert tx_digitalreset after pll_locked goes high. The
tx_digitalreset signal must stay asserted for a minimum t
tx_digitalreset
duration after tx_analogreset is deasserted.
4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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