Intel Cyclone 10 GX User Manual

Figure 222. Power-up Calibration Sequence for Non-PCIe Hard IP (HIP) Channels
For applications not using PCIe Hard IP, the power-up calibration starts from Vreg calibration for all banks and
channels. Then, PreSICE calibration is done in the sequence as shown in the following figure.
Bank 1
Bank 2
ATX PLL Calibration
Bank 1
Bank 2
fPLL Calibration
Bank 1
Bank 2
RX PMA and TX PMA Calibration (1), (2)
After All ATX PLLs Calibrated
After All fPLLs Calibrated
Notes:
(1) CDR/CMU PLL calibration is part of
RX PMA calibration.
(2) For power-up calibration, RX PMA
calibration happens before TX PMA
calibration.
For applications using both PCIe Hard IP and non-PCIe channels, the power-up
calibration sequence is:
1. Vreg calibration for all banks and channels.
2. PCIe Hard IP 0 calibration (if used).
3. Calibration of all non-PCIe Hard IP channels in calibration sequence.
7. Calibration
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English