Intel Cyclone 10 GX User Manual

Name Direction Clock Domain Description
For double width configuration, the following bits are active:
• 40-bit FPGA fabric to PCS interface width: data[103:64],
[39:0]. Ground [127:104], [63:40].
• 64-bit FPGA fabric to PCS interface width: data[127:64],
[63:0].
Double-width mode is not supported for 32-bit, 50-bit, and 67-
bit FPGA fabric to PCS interface widths.
unused_tx_paralle
l_data
Input
tx_clkout
Port is enabled, when you enable Enable simplified data
interface. Connect all of these bits to 0. When Enable
simplified data interface is disabled, the unused bits are a
part of tx_parallel_data. Refer to tx_parallel_data to
identify the bits you need to ground.
tx_control[<n><3>
-1:0] or
tx_control[<n><18
>-1:0]
Input Synchronous to
the clock driving
the write side of
the FIFO
(tx_coreclkin
or tx_clkout)
tx_control bits will have different functionality depending on
the transceiver configuration rule selected. When Simplified
data interface is enabled, the number of bits in this bus will
change, as the unused bits will be shown as part of the
unused_tx_control port.
Refer to Enhanced PCS TX and RX Control Ports on page 59
section for more details.
unused_tx_contro
l[<n> <15>-1:0]
Input Synchronous to
the clock driving
the write side of
the FIFO
(tx_coreclkin
or tx_clkout)
This port is enabled when you enable Enable simplified data
interface. Connect all of these bits to 0. When Enable
simplified data interface is disabled, the unused bits are a
part of the tx_control.
Refer to tx_control to identify the bits you need to ground.
tx_err_ins
Input
tx_coreclkin
For the Interlaken protocol, you can use this bit to insert the
synchronous header and CRC32 errors if you have turned on
Enable simplified data interface.
When asserted, the synchronous header for that cycle word is
replaced with a corrupted one. A CRC32 error is also inserted if
Enable Interlaken TX CRC-32 generator error insertion is
turned on. The corrupted sync header is 2'b00 for a control
word, and 2'b11 for a data word. For CRC32 error insertion, the
word used for CRC calculation for that cycle is incorrectly
inverted, causing an incorrect CRC32 in the Diagnostic Word of
the Metaframe.
Note that a synchronous header error and a CRC32 error
cannot be created for the Framing Control Words because the
Frame Control Words are created in the frame generator
embedded in TX PCS. Both the synchronous header error and
the CRC32 errors are inserted if the CRC-32 error insertion
feature is enabled in the Transceiver Native PHY IP GUI.
tx_coreclkin
Input Clock The FPGA fabric clock. Drives the write side of the TX FIFO. For
the Interlaken protocol, the frequency of this clock could be
from datarate/67 to datarate/32. Using frequency lower than
this range can cause the TX FIFO to underflow and result in
data corruption.
tx_clkout
Output Clock This is a parallel clock generated by the local CGB for non
bonded configurations, and master CGB for bonded
configurations. This clocks the blocks of the TX Enhanced PCS.
The frequency of this clock is equal to the datarate divided by
PCS/PMA interface width.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English