Intel Cyclone 10 GX User Manual

Table 44. Enhanced RX PCS: Parallel Data, Control, and Clocks
Name Direction Clock Domain Description
rx_parallel_data[<n
>128-1:0]
Output Synchronous
to the clock
driving the
read side of
the FIFO
(rx_coreclk
in or
rx_clkout)
RX parallel data from the RX PCS to the FPGA fabric. If you
select, Enable simplified data interface in the Transceiver
Native PHY IP GUI, rx_parallel_data includes only the bits
required for the configuration you specify. Otherwise, this
interface is 128 bits wide.
When FPGA fabric to PCS interface width is 64 bits, the
following bits are active for interfaces less than 128 bits. You
can leave the unused bits floating or not connected.
• 32-bit FPGA fabric to PCS width: data[31:0].
• 40-bit FPGA fabric to PCS width: data[39:0].
• 64-bit FPGA fabric to PCS width: data[63:0].
When the FPGA fabric to PCS interface width is 128 bits, the
following bits are active:
• 40-bit FPGA fabric to PCS width: data[103:64], [39:0].
• 64-bit FPGA fabric to PCS width: data[127:0].
unused_rx_parallel_
data
Output
rx_clkout
This signal specifies the unused data when you turn on Enable
simplified data interface. When simplified data interface is
not set, the unused bits are a part of rx_parallel_data.
You can leave the unused data outputs floating or not
connected.
rx_control[<n>
<20>-1:0]
Output Synchronous
to the clock
driving the
read side of
the FIFO
(rx_coreclk
in or
rx_clkout)
Indicates whether the rx_parallel_data bus is control or
data.
Refer to the Enhanced PCS TX and RX Control Ports on page
59 section for more details.
unused_rx_control[<
n>10-1:0]
Output Synchronous
to the clock
driving the
read side of
the FIFO
(rx_coreclk
in or
rx_clkout)
These signals only exist when you turn on Enable simplified
data interface. When simplified data interface is not set, the
unused bits are a part of rx_control. These outputs can be
left floating.
rx_coreclkin
Input Clock The FPGA fabric clock. Drives the read side of the RX FIFO. For
Interlaken protocol, the frequency of this clock could be from
datarate/67 to datarate/32.
rx_clkout
Output Clock The low speed parallel clock recovered by the transceiver RX
PMA, that clocks the blocks in the RX Enhanced PCS. The
frequency of this clock is equal to data rate divided by
PCS/PMA interface width.
Table 45. Enhanced PCS TX FIFO
Name Direction Clock Domain Description
tx_enh_data_valid[<n>-
1:0]
Input Synchronous to
the clock driving
the write side of
the FIFO
(tx_coreclkin
or tx_clkout)
Assertion of this signal indicates that the TX data is valid.
Connect this signal to 1'b1 for 10GBASE-R without 1588.
For 10GBASE-R with 1588, you must control this signal
based on the gearbox ratio. For Basic and Interlaken, you
need to control this port based on TX FIFO flags so that
the FIFO does not underflow or overflow.
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Send Feedback
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
55

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English