Intel Cyclone 10 GX User Manual

Name Direction Clock Domain Description
Refer to Enhanced PCS FIFO Operation on page 164 for
more details.
tx_enh_fifo_full[<n>-1
:0]
Output Synchronous to
the clock driving
the write side of
the FIFO
(tx_coreclkin
or tx_clkout)
Assertion of this signal indicates the TX FIFO is full.
Because the depth is always constant, you can ignore this
signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 164 for
more details.
tx_enh_fifo_pfull[<n>-
1:0]
Output Synchronous to
the clock driving
the write side of
the FIFO
tx_coreclkin
or tx_clkout
This signal gets asserted when the TX FIFO reaches its
partially full threshold. Because the depth is always
constant, you can ignore this signal for the phase
compensation mode.
Refer to Enhanced PCS FIFO Operation on page 164 for
more details.
tx_enh_fifo_empty[<n>-
1:0]
Output Synchronous to
the clock driving
the write side of
the FIFO
tx_coreclkin
or tx_clkout
When asserted, indicates that the TX FIFO is empty. This
signal gets asserted for 2 to 3 clock cycles. Because the
depth is always constant, you can ignore this signal for
the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 164 for
more details.
tx_enh_fifo_pempty[<n>
-1:0]
Output Synchronous to
the clock driving
the write side of
the FIFO
tx_coreclkin
or tx_clkout
When asserted, indicates that the TX FIFO has reached its
specified partially empty threshold. When you turn this
option on, the Enhanced PCS enables the
tx_enh_fifo_pempty port, which is asynchronous. This
signal gets asserted for 2 to 3 clock cycles. Because the
depth is always constant, you can ignore this signal for
the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 164 for
more details.
Table 46. Enhanced PCS RX FIFO
Name Direction Clock Domain Description
rx_enh_data_valid[<n>
-1:0]
Output Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or rx_clkout
When asserted, indicates that rx_parallel_data is
valid. Discard invalid RX parallel data
whenrx_enh_data_valid signal is low.
This option is available when you select the following
parameters:
• Enhanced PCS Transceiver configuration rules
specifies Interlaken
• Enhanced PCS Transceiver configuration rules
specifies Basic, and RX FIFO mode is Phase
compensation
• Enhanced PCS Transceiver configuration rules
specifies Basic, and RX FIFO mode is Register
Refer to Enhanced PCS FIFO Operation on page 164
for more details.
rx_enh_fifo_full[<n>-
1:0]
Output Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or rx_clkout
When asserted, indicates that the RX FIFO is full. This
signal gets asserted for 2 to 3 clock cycles.Because
the depth is always constant, you can ignore this
signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 164
for more details.
rx_enh_fifo_pfull[<n>
-1:0]
Output Synchronous to
the clock driving
the read side of
When asserted, indicates that the RX FIFO has
reached its specified partially full threshold. This signal
gets asserted for 2 to 3 clock cycles. Because the
depth is always constant, you can ignore this signal
for the phase compensation mode.
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
Send Feedback
56

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English