Intel Cyclone 10 GX User Manual

Parameter Value
Actual PCS TX channel bonding master If TX channel bonding mode is set to PMA and PCS
bonding, then:
0, 1, 2, 3,...,[Number of data channels – 1]
TX local clock division factor If TX channel bonding mode is not bonded, then:
1, 2, 4, 8
Number of TX PLL clock inputs per channel If TX channel bonding mode is not bonded, then:
1, 2, 3, 4
Initial TX PLL clock input selection 0
Enable tx_pma_clkout port On / Off
Enable tx_pma_div_clkout port On / Off
tx_pma_div_clkout division factor When Enable tx_pma_div_clkout port is On, then:
Disabled, 1, 2, 33, 40, 66
Enable tx_pma_elecidle port On / Off
Enable rx_seriallpbken port On / Off
Table 71. RX PMA Parameters
Parameter Value
Number of CDR reference clocks 1 to 5
Selected CDR reference clock 0 to 4
Selected CDR reference clock frequency Select legal range defined by the Quartus Prime software
PPM detector threshold 100, 300, 500, 1000
CTLE adaptation mode manual,
Enable rx_pma_clkout port On / Off
Enable rx_pma_div_clkout port On / Off
rx_pma_div_clkout division factor When Enable rx_pma_div_clkout port is On, then:
Disabled, 1, 2, 33, 40, 66
Enable rx_pma_clkslip port On / Off
Enable rx_is_lockedtodata port On / Off
Enable rx_is_lockedtoref port On / Off
Enable rx_set_locktodata and rx_set_locktoref ports On / Off
Enable rx_seriallpbken port On / Off
Enable PRBS verifier control and status ports On / Off
Table 72. Enhanced PCS Parameters
Parameter Value
Enhanced PCS / PMA interface width 32, 40, 64
FPGA fabric / Enhanced PCS interface width 67
Enable 'Enhanced PCS' low latency mode Allowed when the PMA interface width is 32 and preset
variations for data rate is 10.3125 Gbps or 6.25 Gbps;
otherwise Off
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English