RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 163 of 920
Dec 22, 2016
7.3.7 Timer channel stop register m (TTm)
The TTm register is a trigger register that is used to stop the counting operation of each channel.
When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is
cleared to 0. The TTmn, TTHm1, TTHm3 bits are immediately cleared when operation is stopped (TEmn,
TEHm1, TEHm3 = 0), because they are trigger bits.
The TTm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TTm register can be set with a 1-bit or 8-bit memory manipulation instruction with TTmL.
Reset signal generation clears this register to 0000H.
Figure 7 - 19 Format of Timer channel stop register m (TTm)
Caution Be sure to clear bits 15 to 12, 10, 8 to 4 of the TTm register to “0”.
Remark 1.
When the TTm register is read, 0 is always read.
Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
Address: F01B4H, F01B5H (TT0), F01F4H, F01F5H (TT1) After reset: 0000H R/W
Symbol1514131211109876543210
TTm0000
TTHm
3
0
TTHm
1
0 0 0 0 0 TTm3 TTm2 TTm1 TTm0
TTH
m3
Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
0 No trigger operation
1 TEHm3 bit is cleared to 0 and the count operation is stopped.
TTH
m1
Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
0 No trigger operation
1 TEHm1 bit is cleared to 0 and the count operation is stopped.
TTm
n
Operation stop trigger of channel n
0 TEmn bit is cleared to 0 and the count operation is stopped.
1 Operation is stopped (stop trigger is generated).
This bit is the trigger to stop operation of the lower 8-bit timer for TTm1 and TTm3 when channel 1 or 3 is in the
8-bit timer mode.
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