RL78/G1H CHAPTER 25 REGULATOR
R01UH0575EJ0120 Rev. 1.20 Page 796 of 920
Dec 22, 2016
CHAPTER 25 REGULATOR
25.1 Regulator Overview
The RL78/G1H contains a circuit for operating the device with a constant voltage. At this time, in order to stabilize
the regulator output voltage, connect the REGC pin to V
SS via a capacitor (0.47 to 1 μF). Also, use a capacitor with
good characteristics, since it is used to stabilize internal voltage.
Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
The regulator output voltage, see Table 25 - 1.
Note When it shifts to the subsystem clock operation or STOP mode during the on-chip debugging, the regulator output
voltage is kept at 2.1 V (not decline to 1.8 V).
Table 25 - 1 Regulator Output Voltage Conditions
Mode Output Voltage Condition
LS (low-speed main) mode 1.8 V —
HS (high-speed main) mode 1.8 V In STOP mode
When both the high-speed system clock (f
SUB) and the high-speed on-chip oscillator
clock (f
IH) are stopped during CPU operation with the subsystem clock (fXT)
When both the high-speed system clock (fSUB) and the high-speed on-chip oscillator
clock (f
IH) are stopped during the HALT mode when the CPU operation with the
subsystem clock (f
XT) has been set
2.1 V
Other than above (include during OCD mode)
Note
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