Renesas RL78/G1H

RL78/G1H CHAPTER 6 CLOCK GENERATOR
R01UH0575EJ0120 Rev. 1.20 Page 129 of 920
Dec 22, 2016
6.6.4 CPU clock status transition diagram
Figure 6 - 19 shows the CPU clock status transition diagram of this product.
Figure 6 - 19 CPU Clock Status Transition Diagram
Power ON
Reset release
CPU: Operating
with XT1 oscillation or
EXCLKS input
CPU: Operating
with high-speed
on-chip oscillator
CPU: Operating
with X1 oscillation or
EXCLK input
CPU: High-speed
on-chip oscillator
→ HALT
CPU: X1
oscillation/EXCLK
input → HALT
CPU: X1
oscillation/EXCLK
input → STOP
CPU: High-speed
on-chip oscillator
→ STOP
CPU: High-speed
on-chip oscillator
→ SNOOZE
CPU: XT1
oscillation/EXCLKS
input → HALT
(A)
(B)
(C)
(E)
(J)
(H)
(I)
(F)
(G)
(D)
High-speed on-chip oscillator: Woken up
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation/EXCLKS input: Stops (input port mode)
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation/EXCLKS input: Stops (input port mode)
High-speed on-chip oscillator: Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input:
Oscillatable
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input: Oscillatable
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Oscillatable
XT1 oscillation/EXCLKS input: Oscillatable
High-speed on-chip oscillator: Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input:
Oscillatable
High-speed on-chip oscillator: Oscillatable
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input: Oscillatable
High-speed on-chip oscillator: Selectable by CPU
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input: Selectable by CPU
High-speed on-chip oscillator: Oscillatable
X1 oscillation/EXCLK input: Oscillatable
XT1 oscillation/EXCLKS input: Operating
High-speed on-chip oscillator:
Selectable by CPU
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation/EXCLKS input:
Operating
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Selectable by CPU
XT1 oscillation/EXCLKS input: Selectable by CPU
VDD ≥ Lower limit of the operating voltage range
(release from the reset state triggered by the LVD circuit or an
external reset)