RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 345 of 920
Dec 22, 2016
14.3.10 Serial channel enable status register m (SEm)
The SEm register indicates whether data transmission/reception operation of each channel is enabled or
stopped.
When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1.
When 1 is written a bit of serial channel stop register m (STm), the corresponding bit is cleared to 0.
Channel n that is enabled to operate cannot rewrite by software the value of the CKOmn bit (serial clock output of
channel n) of serial output register m (SOm) to be described below, and a value reflected by a communication
operation is output from the serial clock pin.
Channel n that stops operation can set the value of the CKOmn bit of the SOm register by software and output its
value from the serial clock pin. In this way, any waveform, such as that of a start condition/stop condition, can be
created by software.
The SEm register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the SEm register can be set with a 1-bit or 8-bit memory manipulation instruction with SEmL.
Reset signal generation clears the SEm register to 0000H.
Figure 14 - 16 Format of Serial channel enable status register m (SEm)
Address: F0120H, F0121H (SE0) After reset: 0000H R
Symbol1514131211109876543210
SE0000000000000SE03SE0200
Address: F0160H, F0161H (SE1) After reset: 0000H R
Symbol1514131211109876543210
SE1000000000000SE13SE12SE11SE10
SEm
n
Indication of operation enable/stop status of channel n
0 Operation stops
1 Operation is enabled.
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