RL78/G1H CHAPTER 6 CLOCK GENERATOR
R01UH0575EJ0120 Rev. 1.20 Page 101 of 920
Dec 22, 2016
Remark fX: X1 clock oscillation frequency
f
IH: High-speed on-chip oscillator clock frequency
fEX: External main system clock frequency
f
MX: High-speed system clock frequency
f
MAIN: Main system clock frequency
fXT: XT1 clock oscillation frequency
f
EXS: External subsystem clock frequency
f
SUB: Subsystem clock frequency
fCLK: CPU/peripheral hardware clock frequency
f
IL: Low-speed on-chip oscillator clock frequency
6.3 Registers Controlling Clock Generator
The following registers are used to control the clock generator.
• Clock operation mode control register (CMC)
• System clock control register (CKC)
• Clock operation status control register (CSC)
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
• Peripheral enable registers 0, 1 (PER0, PER1)
• Subsystem clock supply mode control register (OSMC)
• High-speed on-chip oscillator frequency select register (HOCODIV)
• High-speed on-chip oscillator trimming register (HIOTRM)
6.3.1 Clock operation mode control register (CMC)
This register is used to set the operation mode of the X1/P121, X2/EXCLK/P122, XT1/P123, and
XT2/EXCLKS/P124 pins, and to select a gain of the oscillator.
The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release. This
register can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
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