RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 192 of 920
Dec 22, 2016
7.7 Timer Input (TImn) Control
7.7.1 TImn input circuit configuration
A signal is input from a timer input pin, goes through a noise filter and an edge detector, and is sent to a timer
controller.
Enable the noise filter for the pin in need of noise removal. The following shows the configuration of the input
circuit.
Figure 7 - 40 Input Circuit Configuration
7.7.2 Noise filter
When the noise filter is disabled, the input signal is only synchronized with the operating clock (fMCK) for channel
n. When the noise filter is enabled, after synchronization with the operating clock (f
MCK) for channel n, whether
the signal keeps the same value for two clock cycles is detected. The following shows differences in waveforms
output from the noise filter between when the noise filter is enabled and disabled.
Figure 7 - 41 Sampling Waveforms through TImn Input Pin with Noise Filter Enabled and Disabled
Caution The input waveforms to the TImn pin are shown to explain the operation when the noise filter is enabled or
disabled. When actually inputting waveforms, input them according to the TImn input high-level and low-level
widths listed in CHAPTER 31 AC Characteristics.
Noise
filter
Timer
controller
Edge
detection
fTCLK
CCSmn
STSmn2 to
STSmn0
CISmn1,
CISmn0
TNFENmn
TImn pin
f
MCK
Interrupt signal from master channel
Count clock
selection
Trigger
selection
Operating clock (fMCK)
TImn pin
Noise filter disabled
Noise filter enabled
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