RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA
R01UH0575EJ0120 Rev. 1.20 Page 456 of 920
Dec 22, 2016
15.5.7 Canceling wait
The I
2
C usually cancels a wait state by the following processing.
• Writing data to the IICA shift register n (IICAn)
• Setting bit 5 (WRELn) of IICA control register n0 (IICCTLn0) (canceling wait)
• Setting bit 1 (STTn) of the IICCTLn0 register (generating start condition)
Note
• Setting bit 0 (SPTn) of the IICCTLn0 register (generating stop condition)
Note
Note Master only
When the above wait canceling processing is executed, the I
2
C cancels the wait state and communication is
resumed.
To cancel a wait state and transmit data (including addresses), write the data to the IICAn register.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WRELn) of the IICCTLn0
register to 1.
To generate a restart condition after canceling a wait state, set bit 1 (STTn) of the IICCTLn0 register to 1.
To generate a stop condition after canceling a wait state, set bit 0 (SPTn) of the IICCTLn0 register to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to the IICAn register after canceling a wait state by setting the WRELn bit to 1, an
incorrect value may be output to SDAAn line because the timing for changing the SDAAn line conflicts with the
timing for writing the IICAn register.
In addition to the above, communication is stopped if the IICEn bit is cleared to 0 when communication has been
aborted, so that the wait state can be canceled.
If the I
2
C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LRELn) of
the IICCTLn0 register, so that the wait state can be canceled.
Caution If a processing to cancel a wait state is executed when WUPn = 1, the wait state will not be
canceled.
Remark n = 0, 1
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