RL78/G1H CHAPTER 8 TIMER RJ
R01UH0575EJ0120 Rev. 1.20 Page 230 of 920
Dec 22, 2016
8.3.5 Timer RJ mode register 0 (TRJMR0)
The TRJMR0 register sets the operating mode of timer RJ.
The TRJMR0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 8 - 6 Format of Timer RJ mode register 0 (TRJMR0)
Note 1. Do not switch count sources during count operation. Count sources should be switched when both the
TSTART and TCSTF bits in the TRJCR0 register are set to 0 (count stops).
Note 2. When selecting fIL as the count source, set the WUTMMCK0 bit in the subsystem clock supply mode control
register (OSMC) to 1.
However, f
IL cannot be selected as the count source for timer RJ when fSUB is selected as the count source
for the real-time clock or the 12-bit interval timer.
Address: F0242H After Reset: 00H R/W
Symbol76543210
TRJMR0 0 TCK2 TCK1 TCK0 0 TMOD2 TMOD1 TMOD0
TCK2 TCK1 TCK0
Timer RJ count source select
Note 1
000fCLK
001fCLK/8
011f
CLK/2
100
f
IL
Note 2
1 0 1 Event input from ELC
110f
SUB
Other than above Setting prohibited
TMOD2 TMOD1 TMOD0 Timer RJ operating mode select
0 0 0 Timer mode
Other than above Setting prohibited
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