RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 336 of 920
Dec 22, 2016
Figure 14 - 7 Format of Serial mode register mn (SMRmn) (2/2)
Note The SMR03 and SMR13 registers only.
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 (or bits 13 to 6, 4, and 3 for the SMR02, SMR10 to SMR12
register) to “0”. Be sure to set bit 5 to “1”.
14.3.4 Serial communication operation setting register mn (SCRmn)
The SCRmn register is a communication operation setting register of channel n. It is used to set a data
transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit,
start bit, stop bit, and data length.
Rewriting the SCRmn register is prohibited when the register is in operation (when SEmn = 1).
The SCRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets the SCRmn register to 0087H.
Address: F0114H, F0115H (SMR02), F0116H, F0117H (SMR03), After reset: 0020H R/W
F0150H, F0151H (SMR10) to F0156H, F0157H (SMR13)
Symbol1514131211109876543210
SMRmn
CKS
mn
CCS
mn
00000
STS
mn
Note
0
SIS
mn0
Note
1000
MD
mn1
MD
mn0
SIS
mn0
Note
Controls inversion of level of receive data of channel n in UART mode
0 Falling edge is detected as the start bit.
The input communication data is captured as is.
1 Rising edge is detected as the start bit.
The input communication data is inverted and captured.
MD
mn1
Setting of operation mode of channel n
0 CSI mode
1UART mode
MD
mn0
Selection of interrupt source of channel n
0 Transfer end interrupt
1 Buffer empty interrupt
(Occurs when data is transferred from the SDRmn register to the shift register.)
For successive transmission, the next transmit data is written by setting the MDmn0 bit to 1 when SDRmn data has run
out.
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