RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA
R01UH0575EJ0120 Rev. 1.20 Page 448 of 920
Dec 22, 2016
15.4.2 Setting transfer clock by using IICWLn and IICWHn registers
(1) Setting transfer clock on master side
At this time, the optimal setting values of the IICWLn and IICWHn registers are as follows.
(The fractional parts of all setting values are rounded up.)
• When the fast mode
• When the standard mode
• When the fast mode plus
(2) Setting IICWLn and IICWHn registers on slave side
(The fractional parts of all setting values are truncated.)
• When the fast mode
IICWLn = 1.3 μs × f
MCK
IICWHn = (1.2 μs − tR − tF) × fMCK
• When the standard mode
IICWLn = 4.7 μs × f
MCK
IICWHn = (5.3 μs − tR − tF) × fMCK
• When the fast mode plus
IICWLn = 0.50 μs × f
MCK
IICWHn = (0.50 μs − tR − tF) × fMCK
Caution 1.The maximum operating frequency of the IICA operating clock (fMCK) is 20 MHz (Max.). Only
when f
CLK exceeds 20 MHz, set bit 0 (PRSn) of IICA control register n1 (IICCTLn1) to 1.
Caution 2. Note the minimum f
CLK operating frequency when setting the transfer clock. The minimum
fCLK operating frequency for serial interface IICA is determined according to the mode.
Fast mode: f
CLK = 3.5 MHz (MIN.)
Fast mode plus: f
CLK = 10 MHz (MIN.)
Normal mode: f
CLK = 1 MHz (MIN.)
(Remarks are listed on the next page.)
Transfer clock =
f
MCK
IICWL + IICWH + fMCK (tR + tF)
( − tR − tF) × fMCK
IICWLn =
0.52
Transfer clock
× fMCK
IICWHn =
0.48
Transfer clock
( − tR − tF) × fMCK
IICWLn =
0.47
Transfer clock
× fMCK
IICWHn =
0.53
Transfer clock
( − tR − tF) × fMCK
IICWLn =
0.50
Transfer clock
× fMCK
IICWHn =
0.50
Transfer clock
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