To Next Page

To Previous Page

RL78/G1H CHAPTER 21 RESET FUNCTION

R01UH0575EJ0120 Rev. 1.20 Page 752 of 920

Dec 22, 2016

21.2 Register for Confirming Reset Source

21.2.1 Reset control flag register (RESF)

Many internal reset generation sources exist in the RL78 microcontroller. The reset control flag register (RESF)

is used to store which source has generated the reset request.

The RESF register can be read by an 8-bit memory manipulation instruction.

RESET

input, reset by power-on-reset (POR) circuit, and reading the RESF register clear TRAP, WDTRF,

RPERF, IAWRF, and LVIRF flags. To judge the reset source, store RESF register value in the desired RAM, and

use the RAM value for judging.

Figure 21 - 4 Format of Reset control flag register (RESF)

Note 1. The value after reset varies depending on the reset source. See Table 21 - 3.

Note 2. The illegal instruction is generated when instruction code FFH is executed.

Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug

emulator.

Caution 1. Do not read data by a 1-bit memory manipulation instruction.

Caution 2. When enabling RAM parity error resets (RPERDIS = 0), be sure to initialize the used RAM area at data

access or the used RAM area + 10 bytes at execution of instruction from the RAM area.

Reset generation enables RAM parity error resets (RPERDIS = 0). For details, see 24.3.3 RAM parity

error detection function.

Address: FFFA8H After reset: Undefined

Note 1

Symbol76543210

RESF TRAP 0 0 WDTRF 0 RPERF IAWRF LVIRF

TRAP

Internal reset request by execution of illegal instruction

Note 2

0 Internal reset request is not generated, or the RESF register is cleared.