RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS
R01UH0575EJ0120 Rev. 1.20 Page 730 of 920
Dec 22, 2016
19.4.5 Interrupt request hold
There are instructions where, even if an interrupt request is issued while the instructions are being executed,
interrupt request acknowledgment is held pending until the end of execution of the next instruction. These
instructions (interrupt request hold instructions) are listed below.
• MOV PSW, #byte
• MOV PSW, A
• MOV1 PSW. bit, CY
• SET1 PSW. bit
• CLR1 PSW. bit
•RETB
•RETI
• POP PSW
• BTCLR PSW. bit, $addr20
•EI
•DI
• SKC
• SKNC
• SKZ
• SKNZ
• SKH
• SKNH
• MULHU
•MULH
• MACHU
•MACH
• Write instructions for the IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, MK0L, MK0H, MK1L, MK1H, MK2L, MK2H,
PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, and PR12H
registers
Figure 19 - 15 shows the timing at which interrupt requests are held pending.
Figure 19 - 15 Interrupt Request Hold
Remark 1. Instruction N: Interrupt request hold instruction
Remark 2. Instruction M: Instruction other than interrupt request hold instruction
Instruction NCPU processing
××IF
PSW and PC saved,
jump to interrupt servicing
Interrupt servicing
program
Instruction M
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