RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 159 of 920
Dec 22, 2016
7.3.4 Timer status register mn (TSRmn)
The TSRmn register indicates the overflow status of the counter of channel n.
The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count
mode (MDmn3 to MDmn1 = 110B). See Table 7 - 3 for the operation of the OVF bit in each operation mode and
set/clear conditions.
The TSRmn register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the TSRmn register can be set with an 8-bit memory manipulation instruction with TSRmnL.
Reset signal generation clears this register to 0000H.
Figure 7 - 16 Format of Timer status register mn (TSRmn)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
Remark The OVF bit does not change immediately after the counter has overflowed, but changes upon the subsequent capture.
Address: F01A0H, F01A1H (TSR00) to F01A6H, F01A7H (TSR03) After reset: 0000H R
F01E0H, F01E1H (TSR10) to F01E6H, F01E7H (TSR13)
Symbol1514131211109876543210
TSRmn000000000000000OVF
OVF Counter overflow status of channel n
0 Overflow does not occur.
1 Overflow occurs.
When OVF = 1, this flag is cleared (OVF = 0) when the next value is captured without overflow.
Table 7 - 3 OVF Bit Operation and Set/Clear Conditions in Each Operation Mode
Timer operation mode OVF bit Set/clear conditions
• Capture mode
• Capture & one-count mode
clear When no overflow has occurred upon capturing
set When an overflow has occurred upon capturing
• Interval timer mode
• Event counter mode
• One-count mode
clear —
(Use prohibited)
set
To Next Page
Loading...
Need help?
General
