RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 343 of 920
Dec 22, 2016
14.3.8 Serial channel start register m (SSm)
The SSm register is a trigger register that is used to enable starting communication/count by each channel.
When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status
register m (SEm) is set to 1 (Operation is enabled). Because the SSmn bit is a trigger bit, it is cleared
immediately when SEmn = 1.
The SSm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SSm register can be set with an 1-bit or 8-bit memory manipulation instruction with SSmL.
Reset signal generation clears the SSm register to 0000H.
Figure 14 - 14 Format of Serial channel start register m (SSm)
Note If set the SSmn = 1 to during a communication operation, will wait status to stop the communication.
At this time, holding status value of control register and shift register, SCKmn and SOmn pins, and FEFmn,
PEFmn, OVFmn flags.
Caution 1. Be sure to clear bits 15 to 4, 1, and 0 of the SS0 register, and bits 15 to 4 of the SS1 register to “0”.
Caution 2. For the UART reception, set the RXEmn bit of SCRmn register to 1, and then be sure to set SSmn to 1
after 4 or more f
MCK clocks have elapsed.
Remark
When the SSm register is read, 0000H is always read.
Address: F0122H, F0123H (SS0) After reset: 0000H R/W
Symbol1514131211109876543210
SS0000000000000SS03SS0200
Address: F0162H, F0163H (SS1) After reset: 0000H R/W
Symbol1514131211109876543210
SS1000000000000SS13SS12SS11SS10
SSm
n
Operation start trigger of channel n
0 No trigger operation
1
Sets the SEmn bit to 1 and enters the communication wait status
Note
.
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