RL78/G1H CHAPTER 12 WATCHDOG TIMER
R01UH0575EJ0120 Rev. 1.20 Page 277 of 920
Dec 22, 2016
Caution 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows
depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H).
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is cleared to 0 and counting starts.
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is
short, an overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the
STOP mode release by an interval interrupt.
12.4.2 Setting overflow time of watchdog timer
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte
(000C0H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer
starts counting again by writing “ACH” to the watchdog timer enable register (WDTE) during the window open
period before the overflow time.
The following overflow times can be set.
Remark fIL: Low-speed on-chip oscillator clock frequency
Status WDSTBYON = 0 WDSTBYON = 1
In HALT mode Watchdog timer operation stops. Watchdog timer operation continues.
In STOP mode
In SNOOZE mode
Table 12 - 3 Setting of Overflow Time of Watchdog Timer
WDCS2 WDCS1 WDCS0
Overflow Time of Watchdog Timer
(f
IL = 17.25 kHz (MAX.))
000
2
6
/fIL (3.71 ms)
001
2
7
/fIL (7.42 ms)
010
2
8
/fIL (14.84 ms)
011
2
9
/fIL (29.68 ms)
100
2
11
/fIL (118.72 ms)
101
2
13
/fIL (474.89 ms)
110
2
14
/fIL (949.79 ms)
111
2
16
/fIL (3799.18 ms)
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