RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA
R01UH0575EJ0120 Rev. 1.20 Page 439 of 920
Dec 22, 2016
15.3.3 IICA status register n (IICSn)
This register indicates the status of I
2
C.
The IICSn register is read by a 1-bit or 8-bit memory manipulation instruction only when STTn = 1 and during the
wait period.
Reset signal generation clears this register to 00H.
Caution Reading the IICSn register while the address match wakeup function is enabled (WUPn = 1) in
STOP mode is prohibited. When the WUPn bit is changed from 1 to 0 (wakeup operation is
stopped), regardless of the INTIICAn interrupt request, the change in status is not reflected
until the next start condition or stop condition is detected. To use the wakeup function,
therefore, enable (SPIEn = 1) the interrupt generated by detecting a stop condition and read
the IICSn register after the interrupt has been detected.
Remark STTn: bit 1 of IICA control register n0 (IICCTLn0)
WUPn: bit 7 of IICA control register n1 (IICCTLn1)
Figure 15 - 10 Format of IICA status register n (IICSn) (1/3)
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other than the
IICSn register. Therefore, when using the ALDn bit, read the data of this bit before the data of the other bits.
Remark 1. LRELn: Bit 6 of IICA control register n0 (IICCTLn0)
IICEn: Bit 7 of IICA control register n0 (IICCTLn0)
Remark 2. n = 0, 1
Address: FFF51H (IICS0), FFF55H (IICS1) After reset: 00H R
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IICSn MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn
MSTSn Master status check flag
0 Slave device status or communication standby status
1 Master device communication status
Condition for clearing (MSTSn = 0) Condition for setting (MSTSn = 1)
• When a stop condition is detected
• When ALDn = 1 (arbitration loss)
• Cleared by LRELn = 1 (exit from communications)
• When the IICEn bit changes from 1 to 0 (operation stop)
• Reset
• When a start condition is generated
ALDn Detection of arbitration loss
0 This status means either that there was no arbitration or that the arbitration result was a “win”.
1 This status indicates the arbitration result was a “loss”. The MSTSn bit is cleared.
Condition for clearing (ALDn = 0) Condition for setting (ALDn = 1)
• Automatically cleared after the IICSn register is read
Note
• When the IICEn bit changes from 1 to 0 (operation stop)
• Reset
• When the arbitration result is a “loss”.
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