RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 329 of 920
Dec 22, 2016
14.2.1 Shift register
This is an 8-bit register that converts parallel data into serial data or vice versa.
During reception, it converts data input to the serial pin into parallel data.
When data is transmitted, the value set to this register is output as serial data from the serial output pin.
The shift register cannot be directly manipulated by program.
To read or write the shift register, use the lower 8 bits of serial data register mn (SDRmn).
14.2.2 Lower 8 bits of the serial data register mn (SDRmn)
The SDRmn register is the transmit/receive data register (16 bits) of channel n.
Bits 7 to 0 (lower 8 bits) function as a transmit/receive buffer register, and bits 15 to 9 are used as a register that
sets the division ratio of the operation clock (f
MCK).
When data is received, parallel data converted by the shift register is stored in the lower 8 bits. When data is to
be transmitted, set transmit data to be transferred to the shift register to the lower 8 bits.
The data stored in the lower 8 bits of this register is as follows, depending on the setting of bit 0 (DLSmn0) of
serial communication operation setting register mn (SCRmn), regardless of the output sequence of the data.
• 7-bit data length (stored in bits 0 to 6 of SDRmn register)
• 8-bit data length (stored in bits 0 to 7 of SDRmn register)
The SDRmn register can be read or written in 16-bit units.
The lower 8 bits of the SDRmn register can be read or written
Note
as the following SFR, depending on the
communication mode.
• CSIp communication........... SIOp (CSIp data register)
• UARTq reception ................ RXDq (UARTq receive data register)
• UARTq transmission........... TXDq (UARTq transmit data register)
Reset signal generation clears the SDRmn register to 0000H.
Note When operation is stopped (SEmn = 0), do not rewrite SDRmn[7:0] by an 8-bit memory manipulation
instruction (SDRmn[15:9] are all cleared to 0).
Remark After data is received, “0” is stored in bits 0 to 7 in bit portions that exceed the data length.
76543210
Shift register
To Next Page
Loading...
Need help?
General
