RL78/G1H CHAPTER 23 VOLTAGE DETECTOR
R01UH0575EJ0120 Rev. 1.20 Page 764 of 920
Dec 22, 2016
23.4 Operation of Voltage Detector
23.4.1 When used as reset mode
Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the detection voltage (VLVD) by
using the option byte 000C1H.
The operation is started in the following initial setting state when the reset mode is set.
- Bit 7 (LVISEN) of the voltage detection register (LVIM) is set to 0 (disable rewriting of voltage detection level
register (LVIS))
- The initial value of the voltage detection level select register (LVIS) is set to 81H.
Bit 7 (LVIMD) is 1 (reset mode).
Bit 0 (LVILV) is 1 (low-voltage detection level: V
LVD).
• Operation in LVD reset mode
In the reset mode (option byte LVIMDS1, LVIMDS0 = 1, 1), the state of an internal reset by LVD is retained until
the supply voltage (VDD) exceeds the voltage detection level (VLVD) after power is supplied. The internal reset is
released when the supply voltage (V
DD) exceeds the voltage detection level (VLVD).
At the fall of the operating voltage, an internal reset by LVD is generated when the supply voltage (VDD) falls
below the voltage detection level (V
LVD).
Figure 23 - 4 shows the timing of the internal reset signal generated in the LVD reset mode.
To Next Page
Loading...
Need help?
General
