RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC)
R01UH0575EJ0120 Rev. 1.20 Page 523 of 920
Dec 22, 2016
16.3.5 DTC control register j (DTCCRj) (j = 0 to 23)
The DTCCRj register is used to control the DTC operating mode.
Figure 16 - 6 Format of DTC control register j (DTCCRj)
Caution Do not access the DTCCRj register using a DTC transfer.
Address: Refer to 16.3.2 Control Data Allocation. After reset: Undefined R/W
Symbol76543210
DTCCRj 0 SZ RPTINT CHNE DAMOD SAMOD RPTSEL MODE
SZ Transfer Data size selection
08 bits
1 16 bits
RPTINT Enabling/disabling repeat mode interrupts
0 Interrupt generation disabled
1 Interrupt generation enabled
The setting of the RPTINT bit is invalid when the MODE bit is 0 (normal mode).
CHNE Enabling/disabling chain transfers
0 Chain transfers disabled
1 Chain transfers enabled
Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled).
DAMOD Transfer destination address control
0Fixed
1 Incremented
The setting of the DAMOD bit is invalid when the MODE bit is 1 (repeat mode) and the RPTSEL bit is 0 (transfer
destination is the repeat area).
SAMOD Transfer source address control
0Fixed
1 Incremented
The setting of the SAMOD bit is invalid when the MODE bit is 1 (repeat mode) and the RPTSEL bit is 1 (transfer source
is the repeat area).
RPTSEL Repeat area selection
0 Transfer destination is the repeat area
1 Transfer source is the repeat area
The setting of the RPTSEL bit is invalid when the MODE bit is 0 (normal mode).
MODE Transfer mode selection
0 Normal mode
1 Repeat mode
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