Renesas RL78/G1H User Manual

RL78/G1H CHAPTER 12 WATCHDOG TIMER
R01UH0575EJ0120 Rev. 1.20 Page 278 of 920
Dec 22, 2016
12.4.3 Setting window open period of watchdog timer
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option
byte (000C0H). The outline of the window is as follows.
• If “ACH” is written to the watchdog timer enable register (WDTE) during the window open period, the watchdog
timer is cleared and starts counting again.
• Even if “ACH” is written to the WDTE register during the window close period, an abnormality is detected and
an internal reset signal is generated.
Example: If the window open period is 50%
Caution When data is written to the WDTE register for the first time after reset release, the watchdog timer is cleared in
any timing regardless of the window open time, as long as the register is written before the overflow time, and
the watchdog timer starts counting again.
The window open period can be set is as follows.
Note When the window open period is set to 75%, clearing the counter of the watchdog timer (writing ACH to WDTE) must
proceed outside the corresponding period from among those listed below, over which clearing of the counter is prohibited
(for example, confirming that the interval timer interrupt request flag (WDTIIF) of the watchdog timer is set).
Caution When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period is 100% regardless of the
values of the WINDOW1 and WINDOW0 bits.
Table 12 - 4 Setting Window Open Period of Watchdog Timer
WINDOW1 WINDOW0 Window Open Period of Watchdog Timer
0 0 Setting prohibited
0150%
10
75%
Note
1 1 100%
WDCS2 WDCS1 WDCS0
Watchdog timer overflow time
(f
IL = 17.25 kHz (MAX.))
Period over which clearing the
counter is prohibited when the
window open period is set to 75%
000
2
6
/fIL (3.71 ms)
1.85 to 2.51 ms
001
2
7
/fIL (7.42 ms)
3.71 to 5.02 ms
010
2
8
/fIL (14.84 ms)
7.42 to 10.04 ms
011
2
9
/fIL (29.68 ms)
14.84 to 20.08 ms
100
2
11
/fIL (118.72 ms)
56.36 to 80.32 ms
101
2
13
/fIL (474.90 ms)
237.44 to 321.26 ms
110
2
14
/fIL (949.80 ms)
474.89 to 642.51 ms
111
2
16
/fIL (3799.19 ms)
1899.59 to 2570.04 ms
Window close period (50%) Window open period (50%)
Counting
starts
Overflow
time
Internal reset signal is generated
if “ACH” is written to WDTE.
Counting starts again when
“ACH” is written to WDTE.
<R>

Renesas RL78/G1H Specifications

General

Brand	Renesas
Model	RL78/G1H
Category	Microcontrollers
Language	English