RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 340 of 920
Dec 22, 2016
14.3.6 Serial flag clear trigger register mn (SIRmn)
The SIRmn register is a trigger register that is used to clear each error flag of channel n.
When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn,
OVFmn) of serial status register mn is cleared to 0. Because the SIRmn register is a trigger register, it is cleared
immediately when the corresponding bit of the SSRmn register is cleared.
The SIRmn register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SIRmn register can be set with an 8-bit memory manipulation instruction with SIRmnL.
Reset signal generation clears the SIRmn register to 0000H.
Figure 14 - 11 Format of Serial flag clear trigger register mn (SIRmn)
Note The SIR03 and SIR13 registers only.
Caution Be sure to clear bits 15 to 3 (or bits 15 to 2 for the SIR02, SIR10 to SIR12 register) to “0”.
Remark
When the SIRmn register is read, 0000H is always read.
Address: F010CH, F010DH (SIR02), F010EH, F010FH (SIR03), After reset: 0000H R/W
F0148H, F0149H (SIR10) to F014EH, F014FH (SIR13)
Symbol1514131211109876543210
SIRmn0000000000000
FEC
Tmn
Note
PEC
Tmn
OVC
Tmn
FEC
Tmn
Note
Clear trigger of framing error of channel n
0 Not cleared
1 Clears the FEFmn bit of the SSRmn register to 0.
PEC
Tmn
Clear trigger of parity error flag of channel n
0 Not cleared
1 Clears the PEFmn bit of the SSRmn register to 0.
OVC
Tmn
Clear trigger of overrun error flag of channel n
0 Not cleared
1 Clears the OVFmn bit of the SSRmn register to 0.
To Next Page
Loading...
Need help?
General
