RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS
R01UH0575EJ0120 Rev. 1.20 Page 721 of 920
Dec 22, 2016
19.4 Interrupt Servicing Operations
19.4.1 Maskable interrupt request acknowledgment
A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask
(MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if
interrupts are in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request
is not acknowledged during servicing of a higher priority interrupt request.
The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are
listed in Table 19 - 7 below.
For the interrupt request acknowledgment timing, see Figures 19 - 11 and 19 - 12.
Note Maximum time does not apply when an instruction from the internal RAM area is executed.
Remark 1 clock: 1/fCLK (fCLK: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same
priority level, the request with the highest default priority is acknowledged first.
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 19 - 10 shows the Interrupt Request Acknowledgment Processing Algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then
PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged
interrupt are transferred to the ISP1 and ISP0 flags. The vector table data determined for each interrupt request
is the loaded into the PC and branched.
Restoring from an interrupt is possible by using the RETI instruction.
Table 19 - 7 Time from Generation of Maskable Interrupt Until Servicing
Minimum Time
Maximum Time
Note
Servicing time 9 clocks 16 clocks
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