RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA
R01UH0575EJ0120 Rev. 1.20 Page 457 of 920
Dec 22, 2016
15.5.8 Interrupt request (INTIICAn) generation timing and wait control
The setting of bit 3 (WTIMn) of IICA control register n0 (IICCTLn0) determines the timing by which INTIICAn is
generated and the corresponding wait control, as shown in Table 15 - 2.
Note 1. The slave device’s INTIICAn signal and wait period occurs at the falling edge of the ninth clock only when there is a
match with the address set to the slave address register n (SVAn).
At this point, ACK is generated regardless of the value set to the IICCTLn0 register’s bit 2 (ACKEn). For a slave device
that has received an extension code, INTIICAn occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIICAn is generated at the falling edge of the 9th clock, but wait
does not occur.
Note 2. If the received address does not match the contents of the slave address register n (SVAn) and extension code is not
received, neither INTIICAn nor a wait occurs.
Remark The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests and wait control are
both synchronized with the falling edge of these clock signals.
(1) During address transmission/reception
• Slave device operation: Interrupt and wait timing are determined depending on the conditions described
in Notes 1 and 2 above, regardless of the WTIMn bit.
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
the WTIMn bit.
(2) During data reception
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit.
(3) During data transmission
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit.
Remark n = 0, 1
Table 15 - 2 INTIICAn Generation Timing and Wait Control
WTIMn
During Slave Device Operation During Master Device Operation
Address Data Reception
Data
Transmission
Address Data Reception
Data
Transmission
0
9
Notes 1, 2
8
Note 2
8
Note 2
988
1
9
Notes 1, 2
9
Note 2
9
Note 2
999
To Next Page
Loading...
Need help?
General
