RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 149 of 920
Dec 22, 2016
7.3 Registers Controlling Timer Array Unit
Timer array unit is controlled by the following registers.
• Peripheral enable register 0 (PER0)
• Timer clock select register m (TPSm)
• Timer mode register mn (TMRmn)
• Timer status register mn (TSRmn)
• Timer channel enable status register m (TEm)
• Timer channel start register m (TSm)
• Timer channel stop register m (TTm)
• Timer input select register 0 (TIS0)
• Timer output enable register m (TOEm)
• Timer output register m (TOm)
• Timer output level register m (TOLm)
• Timer output mode register m (TOMm)
• Noise filter enable register 1 (NFEN1)
• Port mode register (PMxx)
• Port register (Pxx)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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