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RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC)

R01UH0575EJ0120 Rev. 1.20 Page 525 of 920

Dec 22, 2016

16.3.8 DTC transfer count reload register j (DTRLDj) (j = 0 to 23)

This register is used to set the initial value of the transfer count register in repeat mode. Since the value of this

Figure 16 - 9 Format of DTC transfer count reload register j (DTRLDj)

Caution Do not access the DTRLDj register using a DTC transfer.

16.3.9 DTC source address register j (DTSARj) (j = 0 to 23)

This register is used to specify the transfer source address for data transfer.

When the SZ bit in the DTCCRj register is set to 1 (16-bit transfer), the lowest bit is ignored and the address is

handled as an even address.

Figure 16 - 10 Format of DTC source address register j (DTSARj)

Caution 1. Do not set the general-purpose register (FFEE0H to FFEFFH) space to the transfer source address.

Caution 2. Do not access the DTSARj register using a DTC transfer.

16.3.10 DTC destination address register j (DTDARj) (j = 0 to 23)

This register is used to specify the transfer destination address for data transfer.

When the SZ bit in the DTCCRj register is set to 1 (16-bit transfer), the lowest bit is ignored and the address is

handled as an even address.

Figure 16 - 11 Format of DTC destination address register j (DTDARj)

Caution 1. Do not set the general-purpose register (FFEE0H to FFEFFH) space to the transfer source address.

Caution 2. Do not access the DTDARj register using a DTC transfer.

Address: Refer to 16.3.2 Control Data Allocation. After reset: Undefined R/W

76543210

DTRLDj DTRLDj7 DTRLDj6 DTRLDj5 DTRLDj4 DTRLDj3 DTRLDj2 DTRLDj1 DTRLDj0

Address: Refer to

16.3.2 Control Data Allocation. After reset: Undefined R/W

1514131211109876543210

DTSARj

DTS

ARj15

DTS

ARj14

DTS

ARj13

DTS

ARj12

DTS

ARj11

DTS

ARj10

DTS

ARj9

DTS

ARj8

DTS

ARj7

DTS

ARj6

DTS

ARj5

DTS

ARj4

DTS

ARj3

DTS

ARj2

DTS

ARj1

DTS

ARj0