RL78/G1H CHAPTER 4 CPU ARCHITECTURE
R01UH0575EJ0120 Rev. 1.20 Page 45 of 920
Dec 22, 2016
4.1.2 Mirror area
The code flash area of 00000H to 0FFFFH or 10000H to 1FFFFH, to F0000H to FFFFFH (the code flash area to
be mirrored is set by the processor mode control register (PMC)).
By reading data from F0000H to FFFFFH, an instruction that does not have the ES register as an operand can
be used, and thus the contents of the code flash can be read with the shorter code. However, the code flash area
is not mirrored to the special function register (SFR), extended special function register (2nd SFR), RAM, data
flash memory, and use prohibited areas.
The mirror area can only be read and no instruction can be fetched from this area.
The following show examples.
The PMC register is described below.
• Processor mode control register (PMC)
This register sets the flash memory space for mirroring to area from F0000H to FFFFFH.
The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 4 - 4 Format of Configuration of Processor mode control register (PMC)
Caution After setting the PMC register, wait for at least one instruction and access the mirror area.
Address: FFFFEH After reset: 00H R/W
Symbol7654321<0>
PMC0000000MAA
MAA Selection of flash memory space for mirroring to area from F0000H to FFFFFH
0 00000H to 0FFFFH is mirrored to F0000H to FFFFFH
1 10000H to 1FFFFH is mirrored to F0000H to FFFFFH
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